The present invention relates to a D/A converter using resistors and switches and, more particularly, to a circuit arrangement for minimizing a nonlinear error of a D/A converter which is caused by an ON resistance of a switch.
In a conventional D/A converter of this type using resistors and switches, as shown in FIG. 1, first and second reference voltages VR1 and VR2 are divided by n resistors R. One of (n+1) switches SW connected to each dividing point is turned on by a decoder 51 for converting an input digital signal into a switch drive signal, so that a voltage corresponding to the input digital signal is output from an operational amplifier 52 as an output V.sub.OUT.
Another conventional circuit arrangement is shown in FIG. 2. This D/A converter includes a resistor ladder consisting of resistors R each having a resistance R and resistors 2R each having a resistance 2R, and dual switches 1, 2, . . . , n respectively consisting of switches Cl, C.sub.1, . . . , C.sub.n, C.sub.n. One output electrode of each dual switch is connected to an inverting input terminal (-) of an operational amplifier 62, and the other electrode is connected to the reference voltage VR2 and a non inverting input terminal (+) of the operational amplifier 62. On the other hand, the operational amplifier 62 has a circuit arrangement subjected to resistor feedback by a feedback resistor Rf to convert a current IOUT into a voltage. Signal lines B1 and B2 connected to the input terminals of the operational amplifier 62 are virtually grounded to have potentials equal to the reference voltage VR2. Assume that an ON resistance of the dual switch can be disregarded. Even if the dual switch is connected to one of the two contacts, a resistance is 2R when viewed to the right and in the lower direction with reference to a node An Therefore, I.sub.n1 =I.sub.n2. When simultaneously viewed to the right and in the lower direction from the node An, its composite resistance is R. When viewed from a node A.sub.n-1, a resistance is 2R. Therefore, I.sub.n-1,1 =I.sub.n-2,2.
Similarly, the above result can be obtained in all nodes A.sub.1, A.sub.2, . . . , A.sub.n. Therefore, a current is weighted to 1/2 in the nodes A.sub.1, A.sub.2, . . . , A.sub.n, in the order named, and 2.sup.n combinations can be obtained as the output current I.sub.OUT.
In the above-mentioned conventional D/A converter shown in FIG. 1, however, since a current is not supplied to the switches SW, the ON resistance of the switches can be disregarded. However, the n resistors and (n+1) switches are required in order to perform D/A conversion in (n+1) steps, thus undesirably increasing the number of elements constituting the circuit.
The conventional D/A converter shown in FIG. 2 can perform D/A conversion in 2.sup.n steps by the n dual switches. However, when each dual switch consists of MOS transistors, unbalance occurs due to its ON resistance, thus causing nonlinearity of the D/A conversion characteristics.
For the sake of descriptive simplicity, a 3-bit D/A converter shown in FIG. 3 is exemplified. The same reference numerals in FIG. 3 denote the same parts as in FIG. 2. Reference numeral 63 denotes a drive circuit for driving the dual switches 1 to 3.
In order to minimize the influences of the ON resistances of the three dual switches 1, 2, and 3, normally ON switches 4 and 5 which have ON resistances equal to those of the three dual switches 1, 2, and 3 are connected in series with the resistor R to the right of the node A.sub.3 and with the feedback resistor Rf of the operational amplifier 62 as dummy switches, respectively.
More specifically, assuming that the ON resistance of each dual switch is r, resistances when viewed to the right and in the lower direction from the node A.sub.3 are (2R+r). Therefore, I.sub.31 =I.sub.32.
A composite resistance when simultaneously viewed to the right and in the lower direction from the node A.sub.3, however, is (2R+r)/2=R+r/2. More specifically, a resistance when viewed to the right from the node A.sub.2 is (2R+r/2), and a resistance when viewed in the lower direction from the node A.sub.2 is (2R+r). Therefore, unbalance occurs such that I.sub.21 .noteq.I.sub.22.
Similarly, a resistance when viewed to the right from the node A.sub.1 is (2R+3r/8), and a resistance when viewed in the lower direction from the node A.sub.1 is (2R+r). Therefore, I.sub.11 .noteq.I.sub.12. A degree of the unbalance becomes worse than the relationship between the currents I.sub.21 and I.sub.22. The unbalance between the currents I.sub.11 and I.sub.12 appears as a nonlinear output when control data of the switches 1, 2, and 3 are (1,0,0), and (0,1,1).
FIG. 4 is a graph showing a simulation result obtained by a calculator of the output characteristics of this D/A converter. As is apparent from FIG. 4, a change in error voltage E.sub.OUT is increased when the control data are (0,1,1), and (1,0,0). Therefore, when the D/A converter of 3-bits or more is used, its error becomes a critical problem. In order to prevent the nonlinearity of the error voltage shown in FIG. 4, the ON resistances of the dual switches 2 and 1 must be r/2 and r/4, respectively, if the 0N resistance of the dual switch 3 in FIG. 3 is r. This means that the size of the switch is increased with a power of "2". If a D/A converter of, e.g., 8-bit is used and the size of the smallest switch is "1", the size of the largest switch must be 2.sup.8-1, i.e., 128. As a result, the same problem as that in the circuit shown in FIG. 1 is posed.